The target host does not support the virtual machine’s current hardware requirements. To resolve CPU incompatibilities, use a cluster with Enhanced vMotion Compatibility (EVC) enabled. See KB article 1003212.This CPU does not appear to support AVX instruction sets.
FAIL: 15SU3 virtual machines and higher versions require a physicalCPU that supports the AVX (Advanced Vector Extensions) feature.
This issue occurs due to a mismatch in CPU features between the source and target ESXi hosts. vMotion requires the source and destination hosts to present the same CPU generation feature set to ensure virtual machine stability. If the hosts are in the same cluster but have different microcode versions or hardware generations without a unified EVC baseline, the destination host will reject the virtual machine's active hardware requirements.
To resolve this issue, follow the steps below:
Note: Changes to EVC require a full power-cycle (power off then power on) to take effect on the virtual machine.
For more information, refer How to Configure Per-VM Enhanced vMotion Compatibility in vSphere 8.0
Identify all the CPU models/generation on each ESXi host in the cluster.
For example, under host has a CPU Model of Intel Xeon Gold 6330.
Go to Broadcom Compatibility Guide, select the CPU Series, on left side select Enhanced vMotion Capability Modes, select the appropriate CPU Generation:
Determine the Lowest Common CPU feature compatible on all ESXi hosts in the cluster.
For example, as shown in the above figure, the CPU Model Intel Xeon 6330 supports the following EVC baselines:
Intel® Broadwell (oldest generation)Intel® Cascadelake Intel® HaswellIntel® IcelakeIntel® Ivy-Bridge (newest generation)In the vCenter Server inventory, select the cluster.
Power off all the virtual machines on the hosts with feature sets greater (newer) than the EVC mode.
Click the Configure tab, select VMware EVC, and click Edit.
Enable EVC for the CPU vendor and feature set appropriate for the hosts in the cluster, and click OK.
Power on the virtual machines in the cluster to apply the EVC.
Note: If a new ESXi host is added to the EVC enabled cluster, the ESXi host’s CPU features will reflect the configured baseline features. The ESXi host should be added while in maintenance mode.
For more information, refer CPU Compatibility and EVC
If a processor can support EVC level XN, it can also support levels XN-1 to X0.
For example, a processor that supports the Intel "Sandy Bridge" Generation EVC Baseline has an EVC level of L4 (see Table 1.1). Therefore, it can also support EVC levels L3, L2, L1, and L0. However, it cannot support EVC level L5, which corresponds to the Intel "Ivy Bridge" Generation.
Table 1.1: Description of Intel EVC Baselines
| EVC Level | EVC Baseline | Description |
|---|---|---|
| L0 | Intel "Merom" Gen. (Intel Xeon Core™ 2) | Applies baseline feature set of Intel "Merom" Generation (Intel Xeon Core™ 2) processors to all hosts in the cluster. |
| L1 | Intel "Penryn" Gen. (formerly Intel Xeon 45nm Core™ 2) | Applies baseline feature set of Intel "Penryn" Generation (Intel Xeon 45nm Core™ 2) processors to all hosts in the cluster. Compared to the Intel "Merom" Generation EVC mode, this EVC mode exposes additional CPU features including SSE4.1. |
| L2 | Intel "Nehalem" Gen. (formerly Intel Xeon Core™ i7) | Applies baseline feature set of Intel "Nehalem" Generation (Intel Xeon Core™ i7) processors to all hosts in the cluster. Compared to the Intel "Penryn" Generation EVC mode, this EVC mode exposes additional CPU features including SSE4.2 and POPCOUNT. |
| L3 | Intel "Westmere" Gen. (formerly Intel Xeon 32nm Core™ i7) | Applies baseline feature set of Intel "Westmere" Generation (Intel Xeon 32nm Core™ i7) processors to all hosts in the cluster. Compared to the Intel "Nehalem" Generation mode, this EVC mode exposes additional CPU features including AES and PCLMULQDQ. Note: Intel i3/i5 Xeon Clarkdale Series processors that do not support AESNI and PCLMULQDQ cannot be admitted to EVC modes higher than the Intel "Nehalem" Generation mode. Note: Intel Atom™ C2300-C2700 processors support the Intel "Westmere" Gen. EVC baseline although their architecture is different from the architecture of the Intel "Westmere" Generation processors. |
| L4 | Intel "Sandy Bridge" Generation | Applies baseline feature set of Intel "Sandy Bridge" Generation processors to all hosts in the cluster. Compared to the Intel "Westmere" Generation mode, this EVC mode exposes additional CPU features including AVX and XSAVE. Note: Intel "Sandy Bridge" processors that do not support AESNI and PCLMULQDQ cannot be admitted to EVC modes higher than the Intel "Nehalem" Generation mode. |
| L5 | Intel "Ivy Bridge" Generation | Applies baseline feature set of Intel "Ivy Bridge" Generation processors to all hosts in the cluster. Compared to the Intel "Sandy Bridge" Generation EVC mode, this EVC mode exposes additional CPU features including RDRAND, ENFSTRG, FSGSBASE, SMEP, and F16C. Note: Some Intel "Ivy Bridge" processors do not provide the full "Ivy Bridge" feature set. Such processors cannot be admitted to EVC modes higher than the Intel "Nehalem" Generation mode. |
| L6 | Intel "Haswell" Generation | Applies baseline feature set of Intel "Haswell" Generation processors to all hosts in the cluster. Compared to the Intel "Ivy Bridge" Generation EVC mode, this EVC mode exposes additional CPU features including ABMX2,AVX2, MOVBE, FMA, PERMD, RORX/MULX, INVPCID, VMFUNC. |
| L7 | Intel "Broadwell" Generation | Applies the baseline feature set of Intel "Broadwell" Generation processors to all hosts in the cluster. Compared to the Intel® "Haswell" Generation EVC mode, this EVC mode exposes additional CPU features including Transactional Synchronization Extensions, Supervisor Mode Access Prevention, Multi-Precision Add-Carry Instruction Extensions, PREFETCHW and RDSEED |
| L8 | Intel "Skylake" Generation | Applies the baseline feature set of Intel "Skylake" Generation processors to all hosts in the cluster. Compared to the Intel® "Broadwell" Generation EVC mode,this EVC mode exposes additional CPU features including Advanced Vector Extensions 512, Persistent Memory Support Instructions, Protection Key Rights, Save Processor Extended States with Compaction, and Save Processor Extended States Supervisor |
| L9 | Intel "Cascade Lake" Generation | Applies the baseline feature set of Intel® "Cascade Lake" Generation processors to all hosts in the cluster. Compared to the Intel® "Skylake" Generation EVC mode, this EVC mode exposes additional CPU features including VNNI and XGETBV with ECX = 1. |
| L10 | Intel "Ice Lake" Generation | Applies the baseline feature set of Intel® "Ice Lake" Generation processors to all hosts in the cluster. Compared to the Intel "Cascade Lake" Generation EVC mode, this EVC mode exposes additional CPU features including SHA extensions, Vectorized AES, User Mode Instruction Prevention, Read Processor ID, Fast Short REP MOV, WBNOINVD, Galois Field New Instructions, and AVX512 Integer Fused Multiply Add, Vectorized Bit Manipulation, and Bit Algorithms Instructions |
| L11 | Intel "Sapphire Rapids" Generation | Applies the baseline feature set of Intel® "Sapphire Rapids" Generation processors to all hosts in the cluster. Compared to the Intel® "Ice Lake" Generation EVC mode, this EVC mode exposes additional CPU features, including Control-Flow Enforcement Technology, Advanced Matrix Extensions, Supervisor Protection Keys, AVX-VNNI, AVX512 FP16, AVX512 BF16, CLDEMOTE, SERIALIZE, WBNOINVD, and MOVDIRI instructions. |
Table 1.2: Description of AMD EVC Baselines
| EVC Level | EVC Baseline | Description |
|---|---|---|
| A0 | AMD Opteron™ Generation 1 | Applies baseline feature set of AMD Opteron™ Generation 1 (Rev. E) processors to all hosts in the cluster. |
| A1 | AMD Opteron™ Generation 2 | Applies baseline feature set of AMD Opteron™ Generation 2 (Rev. F) processors to all hosts in the cluster. Compared to the AMD Opteron™ Generation 1 EVC mode, this EVC mode exposes additional CPU features including CPMXCHG16B and RDTSCP. |
| A3 | AMD Opteron™ Generation 3 | Applies baseline feature set of AMD Opteron™ Generation 3 (Greyhound) processors to all hosts in the cluster. Compared to the AMD Opteron™ Generation 2 EVC mode, this EVC mode exposes additional CPU features including SSE4A, MisAlignSSE, POPCOUNT and ABM (LZCNT). Note: Due to 3DNow!™ support being removed from AMD processors after mid 2010, use AMD Opteron™ Generation 3 (no 3DNow!™) when possible to avoid compatibility issues with future processor generations. |
| A2, B0 | AMD Opteron™ Generation 3 (no 3DNow!™) | Applies baseline feature set of AMD Opteron™ Generation 3 (Greyhound) processors with 3DNow!™ support removed, to all hosts in the cluster. This mode allows preparing clusters containing AMD hosts to accept AMD processors without 3DNow!™ support. |
| B1 | AMD Opteron™ Generation 4 | Applies baseline feature set of AMD Opteron™ Generation 4 (Bulldozer) processors to all hosts in the cluster. Compared to the AMD Opteron™ Generation 3 (no 3DNow!™) EVC mode, this EVC mode exposes additional CPU features including SSSE3, SSE4.1, AES, AVX, XSAVE, XOP, and FMA4. |
| B2 | AMD Opteron™ "Piledriver" Generation | Applies baseline feature set of AMD Opteron™ "Piledriver" Generation processors to all hosts in the cluster. Compared to the AMD Opteron™ Generation 4 EVC mode, this EVC mode exposes additional CPU features including FMA, TBM, BMI1, and F16C. |
| B3 | AMD Opteron™ "Steamroller" Generation | Applies baseline feature set of AMD Opteron™ "Steamroller" Generation processors to all hosts in the cluster. Compared to the AMD Opteron™ "Piledriver" EVC mode, this EVC mode exposes additional CPU features including XSAVEOPT RDFSBASE, RDGSBASE, WRFSBASE, WRGSBAS and FSGSBASE. |
| B4 | AMD "Zen" Generation | Applies baseline feature set of AMD "Zen" Generation processors to all hosts in the cluster. Compared to the AMD Opteron™ "Steamroller" EVC mode, this EVC mode exposes additional CPU features including RDRAND, SMEP, AVX2, BMI2, MOVBE, ADX, RDSEED, SMAP, CLFLUSHOPT, XSAVES, XSAVEC, SHA, and CLZERO. |
| B5 | AMD "Zen 2" Generation | Applies the baseline feature set of AMD "Zen 2" Generation processors to all hosts in the cluster. Compared to the AMD "Zen" Generation EVC mode, this EVC mode exposes additional CPU features including CLWB, UMIP, RDPID, XGETBV with ECX = 1, WBNOINVD, and GMET. |
| B6 | AMD "Zen 3" Generation | Applies the baseline feature set of AMD "Zen 3" Generation processors to all hosts in the cluster. Compared to the AMD "Zen 2" Generation EVC mode, this EVC mode exposes additional CPU features, including always serializing LFENCE, INVPCID, PSFD, SSBD, PCID, PKU, VAES, VPCLMULQDQ, and shadow stacks. |
| B7 | AMD 'Zen4" Generation | Applies the baseline feature set of AMD "Zen 4" Generation processors to all hosts in the cluster. Compared to the AMD "Zen 3" Generation EVC mode, this EVC mode exposes additional CPU features including Fast Short CMPSB and STOSB, Automatic IBRS, AVX512BF16, AVX512BITALG, AVX512BW, AVX512CD, AVX512DQ, AVX512F, AVX512IFMA, AVX512VBMI, AVX512VBMI2, AVX512VL, AVX512VNNI, AVX512VPOPCNTDQ, GFNI, IBRS, and Upper Address Ignore. |
If a masked baseline is not required for the immediate migration path (e.g., migrating a VM permanently from an old cluster to a newer cluster where EVC is not yet configured):
OR
If a live vMotion is not possible, perform a Powered-Off migration. This allows the VM to adopt the hardware feature set of the destination host upon the next power-on.
OR