kernel: EDAC MC2: 1 CE memory read error on SV-S550 SSL Visibility Appliance.

Products

SV-S550

Issue/Introduction

You observe the following errors in the SV-S550 SSL Visibility Appliance kern or dmesg logfile.

kernel: EDAC MC2: 1 CE memory read error on CPU_SrcID#1_MC#0_Chan#1_DIMM#0 (channel:1 slot:0 page:0x41023ab offset:0xcc0 grain:32 syndrome:0x0 - err_code:0x0101:0x0091 socket:1 imc:0 rank:0 bg:1 ba:1 row:0xb383 col:0x2a8)

Environment

SV-S550 SSL Visibility Appliance deployed in network topology.

Cause

The error is a single-bit Correctable Error (CE) in memory, detected by the EDAC (Error Detection and Correction) driver on CPU 1, Memory Controller 0, Channel 1, DIMM 0. While automatically corrected, this error may indicate a failing DIMM. This issue may appear to start after a system reboot.

Hardware Effect
As a 1-bit CE, the error is automatically corrected by the ECC hardware, and it generally does not cause system failure. The correction is performed by the memory controller within the same clock cycle as the read (or one extra cycle at most). The correction penalty is minor, roughly 1–2 nanoseconds (0.000001–0.000002 milliseconds), making it invisible at the application level.

Resolution

If this messaging is seen in your SSLV kern and dmesg logs you can attempt rebooting the device to clear the issue. If the issue does not clear please open a case with technical support to see if an RMA is necessary.