Is CA Panvalet zIIP processor enabled? Any plans to zIIP enable CA Panvalet?

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Article ID: 16545

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Updated On:

Products

CA Database Analyzer (IMS Tools) CA Mainframe Configuration Manager for IMS for z/OS IMS TOOLS - MISC CA Compress Data Compression (IMS Tools) CA Database Analyzer for IMS for z/OS CA Database Copier for IMS for z/OS CA Database Organizer for IMS for z/OS CA Mainframe Extended Terminal Manager (IMS Tools) CA High Performance Recovery for IMS for z/OS CA Database Organizer (IMS Tools) CA Mainframe Program Restart Manager for IMS for z/OS CA Secondary Index Builder for IMS for z/OS CA Secondary Index for IMS for z/OS CA JARS CA JARS Resource Accounting CA JARS SMF Director CA JMR CA MIM Resource Sharing (MIM) CA MIM Data Sharing (MII) CA MIM Tape Sharing (MIA) CA MIM Message Sharing (MIC) MIM BASE Nastel AutoPilot for WebSphere MQ CA Panvalet CA QuickFetch CA Raps VSE CA Scheduler VSE CA SMR CA SOLVE:Operations Automation SOLVE:Access Session Management CA SOLVE:CA Mainframe Connector CA SOLVE:FTS CA SYSVIEW Performance Management NXBRIDGE - SYSYVIEW/ENDEVOR CA SOLVE

Issue/Introduction



Is CA Panvalet zIIP processor enabled? Any plans to zIIP enable CA Panvalet?

 

Environment

Release: PVALET00200-14.6-Panvalet
Component:

Resolution

CA Panvalet is not zIIP enabled and does not offload any of the CA Panvalet work from the general CPU processor to a zIIP processor. There are no plans to zIIP enable CA Panvalet. 

There are no plans to zIIP enable CA Panvalet because I/O processing cannot be done from a Service Request Block (SRB) running on a zIIP processor and CA Panvalet processing involves mostly I/O activity such as reading, adding, updating of members in CA Panvalet files. The cost of creating the necessary control blocks and switching back and forth from the general CPU processor to the zIIP processor could actually degrade performance instead of improve performance and increase CPU overhead.